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precision jfet, high speed, dual operational amplifier op249 rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1989C2010 analog devices, inc. all rights reserved. features fast slew rate: 22 v/s typical settling time (0.01%): 1.2 s maximum offset voltage: 200 v typical high open-loop gain: 1000 v/mv minimum low total harmonic distortion: 0.002% typical applications output amplifier for fast dacs signal processing instrumentation amplifiers fast sample-and-holds active filters low distortion audio amplifiers input buffer for adcs servo controllers pin configurations o ut a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 op249 a b 00296-001 figure 1. 8-lead cerdip (q-8) and 8-lead pdip (n-8) +in a 1 v? 2 +in b 3 ?in b 4 ?in a 8 out a 7 v+ 6 out b 5 a b op249 00296-002 figure 2. 8-lead soic (r-8) general description the op249 is a high speed, precision dual jfet op amp, similar to the popular single op amp. the op249 outperforms available dual amplifiers by providing superior speed with excellent dc performance. ultrahigh open-loop gain (1 kv/mv minimum), low offset voltage, and superb gain linearity makes the op249 the industrys first true precision, dual high speed amplifier. with a slew rate of 22 v/s typical and a fast settling time of less than 1.2 s maximum to 0.01%, the op249 is an ideal choice for high speed bipolar dac and adc applications. the excellent dc performance of the op249 allows the full accuracy of high resolution cmos dacs to be realized. symmetrical slew rate, even when driving large load, such as, 600 or 200 pf of capacitance and ultralow distortion, make the op249 ideal for professional audio applications, active filters, high speed integrators, servo systems, and buffer amplifiers. 10 0% 100 90 870ns 500ns 10mv 00296-003 0.01 0 .001 20 100 1k 10k 20k t a = 25c v s = 15v v o = 10v p-p r l = 10k ? a v = 1 00296-004 10 0% 100 90 5v 1s 00296-005 figure 3. fast settling (0.01%) figure 4. low distortion, a v = 1, r l = 10 k figure 5. excellent output drive, r l = 600
op249 rev. g | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? pin configurations ........................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics ............................................................. 3 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? typical performance characteristics ..............................................7 ? applications information .............................................................. 13 ? open-loop gain linearity ....................................................... 14 ? offset voltage adjustment ........................................................ 14 ? settling time ............................................................................... 14 ? dac output amplifier .............................................................. 15 ? discussion on driving adcs ................................................... 16 ? outline dimensions ....................................................................... 17 ? ordering guide .......................................................................... 18 ? revision history 4/10rev. f to rev. g changes to features section and general description section . 1 changes to offset voltage parameter, table 1 .............................. 3 deleted long term offset voltage parameter and note 1, table 1 ................................................................................... 3 c hanges to offset voltage parameter, offset voltage temperature coefficient parameter, and note 1, table 3 ........... 5 delete op249f columns, table 3 ................................................... 5 changes to offset voltage parameter and offset voltage temperature coefficient parameter, table 4 ................................. 5 inserted op249f columns, table 4 ............................................... 5 changes to discussion on driving adcs section ..................... 16 deleted figure 52 and figure 53 ................................................... 17 5/07rev. e to rev. f updated format .................................................................. universal changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to table 3 and table 4 ....................................................... 5 changes to table 5 ............................................................................ 6 changes to figure 31 ...................................................................... 11 changes to figure 37 and figure 38 ............................................. 12 deleted op249 spice macro-model section ............................ 14 deleted figure 18; renumbered sequentially ............................ 14 deleted table i ................................................................................ 15 changes to discussion on driving adcs section ..................... 17 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 19 9/01rev. d to rev. e edits to features and pin connections .......................................... 1 edits to electrical characteristics .............................................. 2, 3 edits to absolute maximum ratings, package type, and ordering guide .................................................................................. 4 deleted wafer test limits and dice characteristics section ...... 5 edits to typical performance characteristics ................................ 8 edits to macro-model figure ........................................................ 15 edits to outline dimensions ......................................................... 17
op249 rev. g | page 3 of 20 specifications electrical characteristics v s = 15 v, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions op249a op249f unit min typ max min typ max offset voltage v os v cm = 0 v 0.2 0.75 0.2 0.9 mv offset stability 1.5 1.5 v/month input bias current i b v cm = 0 v, t a = 25c 30 75 30 75 pa input offset current i os v cm = 0 v, t a = 25c 6 25 6 25 pa input voltage range 1 ivr 12.5 12.5 v 11 11 v ?12.5 C12.5 v common-mode rejection cmr v cm = 11 v 80 90 80 90 db power-supply rejection ratio psrr v s = 4.5 v to 18 v 12 31.6 12 50 v/v large signal voltage gain a vo v o = 10 v, r l = 2 k 1000 1400 500 1200 v/mv output voltage swing v o r l = 2 k 12.5 12.5 v 12.0 12.0 v ?12.5 C12.5 v short-circuit current limit i sc output shorted to ground 36 36 ma 20 50 20 50 ma ?33 C33 ma supply current i sy no load, v o = 0 v 5.6 7.0 5.6 7.0 ma slew rate sr r l = 2 k, c l = 50 pf 18 22 18 22 v/s gain bandwidth product 2 gbw 3.5 4.7 3.5 4.7 mhz settling time t s 10 v step 0.01% 3 0.9 1.2 0.9 1.2 s phase margin m 0 db gain 55 55 degrees differential input impedance z in 10 12 ||6 10 12 ||6 ||pf open-loop output resistance r o 35 35 voltage noise e n p-p 0.1 hz to 10 hz 2 2 v p-p voltage noise density e n f o = 10 hz 75 75 nv/hz f o = 100 hz 26 26 nv/hz f o = 1 khz 17 17 nv/hz f o = 10 khz 16 16 nv/hz current noise density i n f o = 1 khz 0.003 0.003 pa/hz voltage supply range v s 4.5 15 18 4.5 15 18 v 1 guaranteed by cmr test. 2 guaranteed by design. 3 settling time is sample tested.
op249 rev. g | page 4 of 20 v s = 15 v, t a = 25c, unless otherwise noted. table 2. parameter symbol conditions op249g unit min typ max offset voltage v os v cm = 0 v 0.4 2.0 mv input bias current i b v cm = 0 v, t a = 25c 40 75 pa input offset current i os v cm = 0 v t a = 25c 10 25 pa input voltage range 1 ivr 12.5 v 11 v ?12.0 v common-mode rejection cmr v cm = 11 v 76 90 db power supply rejection ratio psrr v s = 4.5 v to 18 v 12 50 v/v large signal voltage gain a vo v o = 10 v; r l = 2 k 500 1100 v/mv output voltage swing v o r l = 2 k 12.5 v 12.0 v ?12.5 v short-circuit current limit i sc output shorted to ground 36 ma 20 50 ma ?33 ma supply current i sy no load; v o = 0 v 5.6 7.0 ma slew rate sr r l = 2 k, c l = 50 pf 18 22 v/s gain bandwidth product 2 gbw 4.7 mhz settling time t s 10 v step 0.01% 0.9 1.2 s phase margin m 0 db gain 55 degree differential input impedance z in 10 12 ||6 ||pf open-loop output resistance r o 35 voltage noise e n p-p 0.1 hz to 10 hz 2 v p-p voltage noise density e n f o = 10 hz 75 nv/hz f o = 100 hz 26 nv/hz f o = 1 khz 17 nv/hz f o = 10 khz 16 nv/hz current noise density i n f o = 1 khz 0.003 pa/hz voltage supply range v s 4.5 15 18 v 1 guaranteed by cmr test. 2 guaranteed by design.
op249 rev. g | page 5 of 20 v s = 15 v, ?55c t a +125c for a grade, unless otherwise noted. table 3. parameter symbol conditions op249a unit min typ max offset voltage v os v cm = 0 v 0.12 1.0 mv offset voltage temperature coefficient tcv os v cm = 0 v 1 10 v/c input bias current 1 i b 4 20 na input offset current 1 i os 0.04 4 na input voltage range 2 ivr 12.5 v 11 v ?12.5 v common-mode rejection cmr v cm = 11 v 76 110 db power supply rejection ratio psrr v s = 4.5 v to 18 v 5 50 v/v large signal voltage gain a vo r l = 2 k; v o = 10 v 500 1400 v/mv output voltage swing v o r l = 2 k 12.5 v 12 v ?12.5 v supply current i sy no load, v o = 0 v 5.6 7.0 ma 1 t a = 125c. 2 guaranteed by cmr test. v s = 15 v, ?40c t a +85c, unless otherwise noted. table 4. parameter symbol conditions op249f op249g unit min typ max min typ max offset voltage v os v cm = 0 v 0.5 1.1 1.0 3.6 mv offset voltage temperature coefficient tcv os v cm = 0 v 2.2 12 6 25 v/c input bias current 1 i b 0.3 4.0 0.5 4.5 na input offset current 1 i os 0.02 1.2 0.04 1.5 na input voltage range 2 ivr 12.5 12.5 v 11 11 v ?12.5 ?12.5 v common-mode rejection cmr v cm = 11 v 80 90 76 95 db power supply rejection ratio psrr v s = 4.5 v to 18 v 7 100 10 100 v/v large signal voltage gain a vo r l = 2 k; v o = 10 v 250 1200 250 1200 v/mv output voltage swing v o r l = 2 k 12.5 12.5 v 12 12.0 v ?12.5 ?12.5 v supply current i sy no load, v o = 0 v 5.6 7.0 5.6 7.0 ma 1 t a = 85c. 2 guaranteed by cmr test.
op249 rev. g | page 6 of 20 absolute maximum ratings table 5. parameter 1 rating supply voltage 18 v input voltage 2 18 v differential input voltage 2 36 v output short-circuit duration indefinite storage temperature range ?65c to +175c operating temperature range op249a (q) ?55c to +125c op249f (q) ?40c to +85c op249g (n, r) ?40c to +85c junction temperature range op249a (q), op249f (q) ?65c to +175c op249g (n, r) ?65c to +150c lead temperature (soldering, 60 sec) 300c 1 absolute maximum ratings apply to packaged parts, unless otherwise noted. 2 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. thermal resistance package type ja 1 jc unit 8-lead cerdip (q) 134 12 c/w 8-lead pdip (n) 96 37 c/w 8-lead soic (r) 150 41 c/w 1 ja is specified for worst-case mounting conditions, that is, ja is specified for device in socket for cerdip and pdip packages; ja is specified for device soldered to printed circui t board for soic package. esd caution
op249 rev. g | page 7 of 20 typical performance characteristics 120 100 80 60 40 20 0 ?20 0 45 90 135 180 225 t a = 25c v s = 15v r l = 2k ? frequency (hz) open-loop gain (db) phase (c) 1k 10k 100k 1m 10m 100m gain phase m = 55 0 0296-006 figure 6. open-loop gain, phase vs. frequency 65 60 45 55 50 10 8 2 6 4 phase margin (c) v s = 15v temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 gain bandwidth product (mhz) gbw m 0 0296-007 figure 7. phase margin, gain bandwidth product vs. temperature 140 120 100 80 60 40 20 0 frequency (hz) 100 1k 10k 100k 1m 10m t a = 25c v s = 15v common-mode rejection (db) 00296-008 figure 8. common-mode rejection vs. frequency 120 100 80 60 40 20 0 t a = 25c v s = 15v +psrr ?psrr power supply rejection (db) frequency (hz) 10 100 1k 10k 100k 1m 00296-009 figure 9. power supply rejection vs. frequency 28 26 24 ?sr 22 20 18 16 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 +sr slew rate (v/s) v s = 15v r l = 2k ? c l = 50pf 00296-010 figure 10. slew rate vs. temperature 28 26 24 22 20 18 16 differential input voltage (v) 0 0.2 0.4 0.6 0.8 1.0 slew rate (v/s) t a = 25c v s = 15v r l = 2k ? 00296-011 figure 11. slew rate vs. differential input voltage
op249 rev. g | page 8 of 20 35 30 25 20 15 10 5 capacitive load (pf) 0 100 200 300 400 500 slew rate (v/s) t a = 25c v s = 15v negative positive 00296-012 figure 12. slew rate vs. capacitive load ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 0.01% 0.01% 0.1% 0.1% t a = 25c v s = 15v a vcl = 1 settling time (ns) 0 200 400 600 800 1000 output step size (v) 00296-013 figure 13. step size vs. settling time 100 80 60 40 20 0 voltage noise density (nv/ hz) t a = 25c v s = 15v frequency (hz) 0 100 1k 10k 00296-014 figure 14. voltage noise density vs. frequency 0.01 0.001 20 100 1k 10k 20k t a = 25c v s = 15v v o = 10v p-p r l = 10k ? a v = 1 00296-015 figure 15. distortion vs. frequency 0.01 0.001 20 100 1k 10k 20k t a = 25c v s = 15v v o = 10v p-p r l = 2k ? a v = 1 00296-016 figure 16. distortion vs. frequency 0.01 0.001 20 100 1k 10k 20k t a = 25c v s = 15v v o = 10v p-p r l = 600 ? a v = 1 00296-017 figure 17. distortion vs. frequency
op249 rev. g | page 9 of 20 0.1 0.01 20 100 1k 10k 20k t a = 25c v s = 15v v o = 10v p-p r l = 10k ? a v = 1 00296-018 figure 18. distortion vs. frequency 0.1 0.01 20 100 1k 10k 20k t a = 25c v s = 15v v o = 10v p-p r l = 2k ? a v = 10 00296-019 figure 19. distortion vs. frequency 0.1 0.01 20 100 1k 10k 20k t a = 25c v s = 15v v o = 10v p-p r l = 600k ? a v = 10 00296-020 figure 20. distortion vs. frequency bandwidth (0.1hz to 10hz) t a = 25c, v s = 15v +1v ?1v 500mv 1s 00296-021 figure 21. low frequency noise 10 0 ?10 60 50 40 30 20 ?20 t a = 25c v s = 15v a vcl = 100 a vcl = 10 a vcl = 5 a vcl = 1 frequency (hz) 1k 10k 100k 1m 10m 100m closed-loop gain (db) 00296-022 figure 22. closed-loop gain vs. frequency 10 0 50 40 30 20 frequency (hz) 100 1k 10k 100k 1m 10m impedance ( ? ) t a = 25c v s = 15v a vcl = 1 a vcl = 10 a vcl = 100 00296-023 figure 23. closed-loop outp ut impedance vs. frequency
op249 rev. g | page 10 of 20 25 20 15 10 0 1k 30 5 1m 10m frequency (hz) output voltage (v p-p) ad8512 ad712 op249 00296-024 figure 24. output voltage vs. frequency 60 50 40 30 20 10 0 70 80 90 load capacitance (pf) 0 100 200 300 400 500 overshoot (%) a vcl = 1 positive edge a vcl = 5 a vcl = 1 negative edge v s = 15v r l = 2k ? v in = 100mv p-p 00296-025 figure 25. small overshoo t vs. load capacitance 14 12 10 8 0 16 6 4 2 load resistance ( ? ) 100 1k 10k maximum output swing (v) +v ohm = |?v ohm | t a = 25c v s = 15v 00296-026 figure 26. maximum output voltage swing vs. load resistance ?20 ?15 ?10 ?5 0 5 10 15 20 0 5 10 15 20 supply voltage (v) output voltage swing (v) t a = 25c r l = 2k ? 00296-027 figure 27. output voltage swing vs. supply voltage 5.2 5.4 5.6 5.8 6.0 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 v s = 15v no load supply current (ma) 00296-028 figure 28. supply current vs. temperature 5.0 5.2 5.4 5.6 5.8 6.0 supply voltage (v) 0 5 10 15 20 supply current (ma) t a = ?55c t a = +125c t a = +25c 00296-029 figure 29. supply current vs. supply voltage
op249 rev. g | page 11 of 20 units 160 180 140 120 100 80 60 40 20 0 ?1000 ?800 ?600 ?400 ?200 0 200 400 600 800 1000 v os (v) t a = 25c v s = 15v 415 op249 (830 op amps) 00296-030 figure 30. v os distribution (n-8) units 240 300 210 180 150 120 90 60 30 0 270 024681012141618202224 tcv os (v/c) v s = 15v ?40c to +85c (830 op amps) 00296-031 figure 31. tcv os distribution (n-8) 50 20 30 0 40 10 time after power applied (minutes) 01234 offset voltage (v) 5 v s = 15v 00296-032 figure 32. offset voltage warm-up drift 100 1k 10k 10 1 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 v s = 15v v cm = 0v input bias current (pa) 00296-033 figure 33. input bias current vs. temperature common-mode voltage (v) ?15 ?10 ?5 0 5 10 15 10 4 10 3 10 2 10 1 10 0 t a = 25c v s = 15v bias current (pa) 00296-034 figure 34. bias current vs. common-mode voltage 50 20 30 0 40 10 input bias current (pa) t a = 25c v s = 15v time after power applied (minutes) 02468 00296-035 1 0 figure 35. bias current warm-up drift
op249 rev. g | page 12 of 20 80 20 0 40 60 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 input offset current (pa) t a = 25c v cm = 0v 00296-036 figure 36. input offset current vs. temperature 12000 4000 2000 0 6000 8000 10000 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 open-loop gain (v/mv) v s = 15v r l = 10k ? r l = 2k ? 00296-037 figure 37. open-loop gain vs. temperature 80 20 0 40 60 sink short-circuit output current (ma) v s = 15v temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 source 00296-038 figure 38. short-circuit output current vs. junction temperature
op249 rev. g | page 13 of 20 applications information +in v + v out v? ?in 0 0296-039 figure 39. simplified schematic (1/2 op249) +3v +18v +3v 5k ? 5k ? 1/2 op249 1/2 op249 2 1 3 6 5 4 8 7 ?18v 0 0296-040 figure 40. burn-in circuit the op249 represents a reliable jfet amplifier design, featuring an excellent combination of dc precision and high speed. a rugged output stage provides the ability to drive a 600 load and still maintain a clean ac response. the op249 features a large signal response that is more linear and symmetric than previously available jfet input amplifiers. figure 41 compares the large signal response of the op249 to other industry-standard dual jfet amplifiers. typically, the slewing performance of the jfet amplifier is specified as a number of v/s. there is no discussion on the quality, that is, linearity and symmetry of the slewing response. 10 0% 100 90 a) op249 10 0% 100 90 b) lt1057 10 0% 100 90 c) ad712 1s 5v 1s 5v 1s 5v 00296-041 figure 41. large-signal transient response, a v = 1, v in = 20 v p-p, z l = 2 k//200 pf, v s = 15 v the op249 was carefully designed to provide symmetrically matched slew characteristics in both the negative and positive directions, even when driving a large output load. the slewing limitation of the amplifier determines the maximum frequency at which a sinusoidal output can be obtained without significant distortion. however, it is important to note that the nonsymmetric slewing typical of previously available jfet amplifiers adds a higher series of harmonic energy content to the resulting responseand an additional dc output component. examples of potential problems of nonsymmetric slewing behavior can be in audio amplifier applications, where a natural low distortion sound quality is desired and in servo or signal processing systems where a net dc offset cannot be tolerated. the linear and symmetric slewing feature of the op249 makes it an ideal choice for applications that exceed the full power bandwidth range of the amplifier.
op249 rev. g | page 14 of 20 10 0% 100 90 50mv 1s 00296-042 figure 42. small-signal transient response, a v = 1, z l = 2 k||100 pf, no compensation, v s = 15 v as with most jfet input amplifiers, the output of the op249 can undergo phase inversion if either input exceeds the specified input voltage range. phase inversion does not damage the amplifier, nor does it cause an internal latch-up condition. supply decoupling should be used to overcome inductance and resistance associated with supply lines to the amplifier. a 0.1 f and a 10 f capacitor should be placed between each supply pin and ground. open-loop gain linearity the op249 has both an extremely high open-loop gain of 1 kv/mv minimum and constant gain linearity, which enhances its dc precision and provides superb accuracy in high closed-loop gain applications. figure 43 illustrates the typical open-loop gain linearityhigh gain accuracy is assured, even when driving a 600 load. offset voltage adjustment the inherent low offset voltage of the op249 makes offset adjustments unnecessary in most applications. however, where a lower offset error is required, balancing can be performed with simple external circuitry, as shown in figure 44 and figure 45 . horizontal 5v/div output charge vertical 50v/div input variation 00296-043 figure 43. open-loop gain linearity; variation in open-loop gain results in errors in high closed-loop gain circuits; r l = 600 , v s = 15 v +v r3 r4 r2 r1 v os adjust range = v v out v in ?v 1/2 op249 r2 31? r5 5 0k? r1 200k? 00296-044 figure 44. offset adjustment for inverting amplifier configuration + v r5 v os adjust range = v r2 r1 1 + r5 r4 if r2 << r4 r5 r4 + r2 r4 v out ?v v in r3 50k? r2 33? r1 200k ? 1/2 op249 gain = = 1 + v out v in = 00296-045 figure 45. offset adjustment for no ninverting amplif ier configuration in figure 44 , the offset adjustment is made by supplying a small voltage at the noninverting input of the amplifier. resistors r1 and r2 attenuate the potentiometer voltage, providing a 2.5 mv (with v s = 15 v) adjustment range, referred to the input. figure 45 shows the offset adjustment for the noninverting amplifier configuration, also providing a 2.5 mv adjustment range. as shown in the equations in figure 45 , if r4 is not much greater than r2, a resulting closed-loop gain error must be accounted for. settling time the settling time is the time between when the input signal begins to change and when the output permanently enters a prescribed error band. the error bands on the output are 5 mv and 0.5 mv, respectively, for 0.1% and 0.01% accuracy. figure 46 shows the settling time of the op249, which is typically 870 ns. moreover, problems in settling response, such as thermal tails and long-term ringing, are nonexistent. 10 0% 100 90 500ns 10mv 870ns 00296-046 figure 46. settling characteristics of the op249 to 0.01%
op249 rev. g | page 15 of 20 dac output amplifier because the dac output capacitance appears at the inputs of the op amp, it is essential that the amplifier be adequately compensated. compensation increases the phase margin and ensures an optimal overall settling response. the required lead compensation is achieved with capacitor c in figure 48 . unity-gain stability, a low offset voltage of 300 v typical, and a fast settling time of 870 ns to 0.01%, makes the op249 an ideal amplifier for fast dacs. for cmos dac applications, the low offset voltage of the op249 results in excellent linearity performance. cmos dacs, such as the pm7545, typically have a code-dependent output resistance variation between 11 k and 33 k. the change in output resistance, in conjunction with the 11 k feedback resistor, results in a noise gain change, which causes variations in the offset error, increasing linearity errors. the op249 features low offset voltage error, minimizing this effect and maintaining 12-bit linearity performance over the full-scale range of the converter. +15v pm7545 12 500? 75? agnd dgnd data input reference or v in v dd 0.1f v out v dd r fb out 1 db 11 to db 0 19 18 20 3 v ref c 33pf ?15v 1 2 3 2 8 4 0.1f 0.1f 1 1/2 op249 00296-047 figure 47. fast settling and low offset error of the op249 enhances cmos dac performanceunipolar operation +15v pm7545 500? 75 ? agnd dgnd 12 data input v out 0.1f ?15v 1/2 op249 1/2 op249 7 5 6 4 r5 10k ? 1% r4 20k ? 1% r3 10k? 1% 1 8 2 3 1 2 3 0.1f c 33pf v dd 0.1f reference or v in db 11 to db 0 out 1 r fb v dd v ref 18 20 19 00296-048 figure 48. fast settling and low offset error of the op249 enhances cmos dac performancebipolar operation
op249 rev. g | page 16 of 20 10 0% 100 90 500mv 1s 4s 10 0% 100 90 500mv 1s 4s a c = 5pf response is grossly underdamped, and exhibits ringing b c = 15pf fast rise time characteristics, but at expense of slight peaking in response 00296-049 figure 49. effect of altering compensation from circuit in figure 47 pm7545 cmos dac with 1/2 op249, unipolar operation; critically damped response is obtained with c 33 pf figure 49 illustrates the effect of altering the compensation on the output response of the circuit in figure 47 . compensation is required to address the combined effect of the output capacitance of the dac, the input capacitance of the op amp, and any stray capacitance. slight adjustments to the compensation capacitor may be required to optimize settling response for any given application. the settling time of the combination of the current output dac and the op amp can be approximated by ()( ) 2 2 amptdact totalt s s s + = the actual overall settling time is affected by the noise gain of the amplifier, the applied compensation, and the equivalent input capacitance at the input of the amplifier. discussion on driving adcs settling characteristics of op amps also include the ability of the amplifier to recover, that is, settle, from a transient current output load condition. an example of this includes an op amp driving the input from a sar-type adc. although the comparison point of the converter is usually diode clamped, the input swing of plus-and-minus a diode drop still gives rise to a significant modulation of input current. if the closed-loop output impedance is low enough and bandwidth of the amplifier is sufficiently large, the output settles before the converter makes a comparison decision, which prevents linearity errors or missing codes. figure 50 shows a settling measurement circuit for evaluating recovery from an output current transient. an output disturbing current generator provides the transient change in output load current of 1 ma. +15 v +15v 1.5k ? 1n4148 220? 1.8k ? 2n3904 1k? * * t tl input +15v 2n2907 7a13 plug-in 7a13 plug-in 300pf 1/2 op249 + 1k ? |v ref | ? i out = ?15v 0.1f 0.1f 0.1f 10f v ref 0.01f 1k? 0.47f 3 2 8 1 4 * decouple close together on ground plane with short lead lengths. 00296-050 figure 50. transient output impedance test fixture as seen in figure 51 , the op249 has an extremely fast recovery of 247 ns (to 0.01%) for a 1 ma load transient. the performance makes it an ideal amplifier for data acquisition systems. 10 0% 100 90 100ns 2v 2mv 247.4ns 00296-051 figure 51. transient recovery time of the op249 from a 1 ma load transient to 0.01%
op249 rev. g | page 17 of 20 outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 52. 8-lead plastic dual in-line package [pdip] narrow body (n-8) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 53. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches)
op249 rev. g | page 18 of 20 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.055 (1.40) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 14 5 8 figure 54. 8-lead ceramic dual in-line package [cerdip] (q-8) dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option op249az ?55c to +125c 8-lead cerdip q-8 op249fz ?40c to +85c 8-lead cerdip q-8 op249gp ?40c to +85c 8-lead pdip n-8 OP249GPZ ?40c to +85c 8-lead pdip n-8 op249gs ?40c to +85c 8-lead soic_n r-8 op249gs-reel ?40c to +85c 8-lead soic_n r-8 op249gs-reel7 ?40c to +85c 8-lead soic_n r-8 op249gsz ?40c to +85c 8-lead soic_n r-8 op249gsz-reel ?40c to +85c 8-lead soic_n r-8 op249gsz-reel7 ?40c to +85c 8-lead soic_n r-8 1 z = rohs compliant part. for military processed devices, see the standard microcircuit drawings (smd) available at www.dscc.dla.mil/programs/milspec/def ault.asp. table 7. smd part number analog devices, inc. equivalent 5962-9151901m2a op249arcmda 5962-9151901mpa op249azmda
op249 rev. g | page 19 of 20 notes
op249 rev. g | page 20 of 20 notes ?1989C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00296-0-4/10(g)

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